SK Hynix announced its strategic plans for next-generation DRAM technology at the IEEE VLSI Symposium 2025 held in Kyoto, Japan, showcasing a forward-looking innovation blueprint for the next 30 years.
The symposium, running from June 8 to 12, featured SK Hynix's keynote speech on June 10 (local time), where the company unveiled its roadmap for future DRAM technologies. During the event, CTO Cha Soon-yong delivered a speech titled "Innovating DRAM for a Sustainable Future," sharing key strategies to surpass current technological limitations.
CTO Cha emphasized that “the traditional process technology platforms based on finer nodes are reaching performance and density limits,” and announced plans to accelerate structural innovations centered around the 10-nanometer class process, including the development of the 4F² VG platform and 3D DRAM technologies.
The 4F² VG platform, characterized by a revolutionary reduction in cell area and vertical transistor gate structures, is regarded as a next-generation DRAM capable of high speed, low power consumption, and high density. It offers higher integration than the currently commercialized 6F² cell, with additional improvements in electrical performance achieved through wafer bonding technology that stacks circuits underneath cells.
Furthermore, CTO Cha outlined the development direction for 3D DRAM. Despite concerns over increased manufacturing costs associated with high-capacity stacking processes, SK Hynix plans to overcome these challenges through process efficiency enhancements and material innovations, thus securing market competitiveness.
The company also stressed its commitment to advancing material and device technologies involved in DRAM to lay a foundation for sustainable technological evolution over the coming decades.
CTO Cha stated, “While there was talk that the 20-nanometer process was the limit for DRAM, continuous technological innovation has allowed us to surpass it,” and added, “We will present a long-term technological vision that challenges our young engineers, and open a new era for DRAM through industry collaboration.”
On the final day of the symposium, Vice President Park Joo-dong, in charge of the Next-Generation DRAM Task Force, is expected to present the latest research achievements demonstrating the electrical properties of DRAM utilizing VG and wafer bonding technologies.
